Integrated circuits are used in many portable electronic products, such as cell phones, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc. Across virtually all applications, there continues to be demand for reducing the size and increasing performance of the devices. The intense demand is no more visible than in portable electronics that have become so ubiquitous.
As the demand for smaller electronic devices grows, manufacturers are seeking ways to reduce the size and weight of the packaged integrated circuits. To meet these needs, packaging technologies are shifting towards thinner profiles with more die stacking and/or wafer level packaging in bare die form. This drives the demand for better wafer thinning technology to achieve a very thin wafer thickness.
Existing technology has attempted to significantly reduce wafer stress during wafer thinning processes so that higher wafer production can be achieved. In addition to reducing wafer stress, some attempts also address wafer strength during processing hoping to avoid the effects of wafer stress. Technologies such as Dicing Before Backgrind (DBG), Etching (Dry or Wet), Plasma, Polishing (Dry or Wet) are some of the attempts adopted by various companies and industries to obtain an ultra thin wafer thickness.
However, these technologies can only reduce wafer stress within the wafer itself. The extreme edge of the original wafer (i.e. before grind) is rounded. When the wafer is ground ultra thin, this edge will be reduced to an extremely sharp edge, which is extremely weak. At a micro-level view, it can be observed that there is not any form of “support” at this part of the wafer. Hence, any application of uneven force during grinding or stress relieving can easily create a crack. This crack can continue to spread during further handling and cause wafer edge chipping or even wafer cracking. Because of the failure mechanism described, the existing wafer thinning technology will not able to provide a solution to prevent failures from occurring at the edge of the wafer.
Thus a need still remains for a wafer strength reinforcement system for ultra thin wafer thinning to provide thinner wafer profiles while reducing wafer stress and improving wafer strength, particularly at the edge of the wafer. In view of the increasing demand for improved density of integrated circuits and particularly portable electronic products, it is increasingly critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.